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| LEADER |
00000cam a2200000 7i4500 |
| 001 |
0000022262 |
| 005 |
20070202.0 |
| 008 |
070131s2006 |
| 090 |
0 |
0 |
|a D621.38928
|b MOH
|
| 100 |
1 |
0 |
|a Mohd Fasha b. Abd Razak
|
| 245 |
1 |
0 |
|a Peranti masukan dan keluaran 8Bit dengan menggunakan FPGA :
|b Mohd Fasha b. Abd Razak
|
| 260 |
0 |
0 |
|a Penang :
|b Universiti Sains Malaysia ,
|c 2006
|
| 300 |
|
|
|a xii, 79p. ;
|c 29cm.
|
| 502 |
0 |
0 |
|a Thesis (Sarjana Kejuruteraan).-Universiti Sains Malaysia
|
| 610 |
2 |
0 |
|a Universiti Sains Malaysia
|x Dissertation
|
| 650 |
0 |
0 |
|a Electronic circuit design
|
| 650 |
0 |
0 |
|a System design
|x Data processing
|
| 650 |
0 |
0 |
|a VHDL(Computer hardware description language)
|
| 999 |
|
|
|a D000007792
|b THESIS AND DISSERTATIONS
|c REFERENCE
|e Default branch
|