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| LEADER |
00000cam a2200000 7i4500 |
| 001 |
0000023801 |
| 005 |
20070711.0 |
| 008 |
070711s2007 |
| 100 |
1 |
0 |
|a WONG Weng Yew
|
| 245 |
1 |
2 |
|a A Computer Modelling of Wrapper Redundancy Logic for MBISR
|c Wong Weng Yew
|
| 260 |
0 |
0 |
|a Serdang :
|b Universiti Tenaga Nasional ,
|c 2007
|
| 300 |
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|a xii71p., :
|b ill., ;
|c 30cm.
|
| 502 |
0 |
0 |
|a Thesis (Bachelor of Electrical and Electronics Engineering)-Universiti Tenaga Nasional, 2007
|
| 610 |
2 |
0 |
|a Universiti Tenaga Nasional
|x Dissertation
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| 999 |
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|a D000008706
|b THESIS AND DISSERTATIONS
|c REFERENCE
|e Default branch
|